M28010 datasheet(4/23 Pages) STMICROELECTRONICS

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M28010

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Table 3. Operating Modes 1

Note: 1. X = VIH or VIL.

Mode

DQ0-DQ7

Read

VIL

VIH

Data Out

Write

VIL

VIH

VIL

Data In

Stand-by / Write Inhibit

VIH

Hi-Z

Write Inhibit

VIH

Data Out or Hi-Z

Write Inhibit

VIL

Data Out or Hi-Z

Output Disable

VIH

Hi-Z

Write Enable (W). The Write Enable input controls

whether the addressed location is to be read, from

or written to.

DEVICE OPERATION

In order to prevent data corruption and inadvertent

write operations, an internal VCC comparator

inhibits the Write operations if the VCC voltage is

lower than VWI (see Table 4A to Table 4C). Once

the voltage applied on the VCC pin goes over the

VWI threshold (VCC>VWI), write access to the

memory is allowed after a time-out tPUW,as

specified in Table 4A to Table 4C.

Further protection against data corruption is

offered by the E and W low pass filters: any glitch,

on the E and W inputs, with a pulse width less than

10 ns (typical) is internally filtered out to prevent

inadvertent write operations to the memory.

Table 4A. Power-Up Timing

1 for M28010 (5V range)

(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)

Note: 1. Sampled only, not 100% tested.

Table 4B. Power-Up Timing1 for M28010-W (3V range)

(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)

Note: 1. Sampled only, not 100% tested.

Table 4C. Power-Up Timing1 for M28010-R (2V range)

(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)

Note: 1. Sampled only, not 100% tested.

Symbol

Parameter

Min.

Max.

Unit

tPUR

Time Delay to Read Operation

tPUW

Time Delay to Write Operation (once VCC ≥ VWI)

5ms

VWI

Write Inhibit Threshold

3.0

4.2

Symbol

Parameter

Min.

Max.

Unit

tPUR

Time Delay to Read Operation

tPUW

Time Delay to Write Operation (once VCC

≥ VWI)5

VWI

Write Inhibit Threshold

2.0

2.6

Symbol

Parameter

Min.

Max.

Unit

tPUR

Time Delay to Read Operation

tPUW

Time Delay to Write Operation (once VCC

≥ VWI)5

VWI

Write Inhibit Threshold

1.2

1.7

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