M41ST85Y datasheet(11/34 Pages) STMICROELECTRONICS

No. de pieza	M41ST85Y

Descripción Electrónicos	5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR

PDF	34 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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M41ST85Y, M41ST85W

Figure 13. Alternate READ Mode Sequence

WRITE Mode

In this mode the master transmitter transmits to

the M41ST85Y/W slave receiver. Bus protocol is

shown in Figure 14., page 11. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to the ad-

dressed device that word address An will follow

and is to be written to the on-chip address pointer.

The data word to be written to the memory is

strobed in next and the internal address pointer is

incremented to the next memory location within

the RAM on the reception of an acknowledge

clock. The M41ST85Y/W slave receiver will send

an acknowledge clock to the master transmitter af-

ter it has received the slave address (see Figure

11., page 10) and again after it has received the

word address and each data byte.

Figure 14. WRITE Mode Sequence

AI00895

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

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