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LRI64 Datasheet(PDF) 13 Page - STMicroelectronics

No. de pieza LRI64
Descripción Electrónicos  Memory tag IC at 13.56 MHz, with 64-bit unique ID and WORM user area, ISO 15693 and ISO 18000-3 Mode 1 compliant
PDF  52 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LRI64 Datasheet(HTML) 13 Page - STMicroelectronics

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LRI64
VCD to LRI64 frames
13/52
7
VCD to LRI64 frames
Request frames are delimited by a start of frame (SOF) and an end of frame (EOF) and are
implemented using a code violation mechanism. Unused options are reserved for future
use.
The LRI64 is ready to receive a new command frame from the VCD after a delay of t2 (see
Table 14) after having sent a response frame to the VCD.
The LRI64 generates a power-on delay of tPOR (see Table 14) after being activated by the
powering field. After this delay, the LRI64 is ready to receive a command frame from the
VCD.
In ISO 15693 and ISO 18000-3 Mode 1 standards, the SOF is used to define the data
coding mode that the VCD is going to use in the following command frame.
The SOF that is shown in Figure 7 selects the “1-out-of-4” data coding mode. (The LRI64
does not support the SOF for the “1-out-of-256” data coding mode.)
The corresponding EOF sequence is shown in Figure 8.
Figure 7.
Request SOF, using the “1-out-of-4” data coding mode
Figure 8.
Request EOF
AI06660
37.76 µs
9.44 µs
9.44 µs
37.76 µs
9.44 µs
AI06662
9.44 µs
37.76 µs
9.44 µs



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