M54HCT137

M74HCT137

February 1993

3 TO 8 LINE DECODER/LATCH (INVERTING)

B1R

(Plastic Package)

ORDER CODES :

M54HCT137F1R

M74HCT137M1R

M74HCT137B1R

M74HCT137C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

COMPATIBLE WITH TTL OUTPUTS

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS137

The M54/74HCT137 is a high speed CMOS3TO8LINE

DECODER/LATCH (INVERTING) fabricated in silicon

gateC

formance ofLSTTL combined with trueCMOSlow power

consumption. This device is a 3 to 8 line decoder with lat-

ches onthe three address inputs. When GLgoes from low

to high, the address present at the select inputs (A, B and

C) is stored in the latches. As long as GLremains high no

address changes will be recognized. Output enable pins

G1 and G2, control the state of the outputs independently

ofthe select or latch-enable inputs. All theoutputs are high

unless G1 is high and G2 is low. The HC137 is ideally

suited for the implementation of glitch-free decoders in

stored-address applications in bus oriented systems. All

inputs are equipped with protection circuits against static

discharge and transient excess voltage.This integrated

circuit has input and output characteristics that are fully

compatible with 54/74 LSTTL logic families. M54/74HCT

devices aredesigned todirectly interfaceHSC

tems with TTL and NMOS components. They are also

plug in replacements for LSTTL devices giving a re-

duction of power consumption.

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