R7KA8M2AFDCAM datasheet(82/295 Pages) RENESAS

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Table 2.34

Coremark and normal mode current, CPU0 active, CPU1 Deep Sleep. (DCDC mode and External VDD

mode) (2 of 2)

Parameter

Symbol Typ

Max

Unit Test conditions

°C

105

°C

125

°C

Supply

current*1*2

CPUCLK0 =

600 MHz

CPUCLK1 =

200 MHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

IDD

172

—

μA/

CPU1 = Deep Sleep

ESWM power domain off

CPUCLK1 = 200 MHz,

MRICLK = 200 MHz,

MRPCLK = 25 MHz, ICLK

= 200 MHz, PCLKA = 25

MHz, PCLKB = 25 MHz,

PCLKC = 25 MHz, PCLKD

= 25 MHz, PCLKE = 25

MHz, BCLK = 25 MHz

Cache off,

executing from

ITCM

164

—

Cache off,

executing from

SRAM

118

—

Cache off,

executing from

MRAM

133

—

Normal

mode

All peripheral

disabled, Cache

on, while (1) code

139

—

All peripheral

disabled, Cache

off, while (1) code

executing from

MRAM

142

—

CPUCLK0 =

600 MHz

VSCR_2

VCL =

voltage

range 2

Coremark

Cache on

164

—

μA/

CPU1 = Deep Sleep

ESWM power domain off

CPUCLK1 = 150 MHz,

MRICLK = 150 MHz,

MRPCLK = 9.4 MHz, ICLK

= 150 MHz, PCLKA =

9.4 MHz, PCLKB = 9.4

MHz, PCLKC = 9.4 MHz,

PCLKD = 9.4 MHz, PCLKE

= 9.4 MHz, BCLK = 9.4

MHz

Cache off,

executing from

ITCM

156

—

Cache off,

executing from

SRAM

106

—

Cache off,

executing from

MRAM

119

—

Normal

mode

All peripheral

disabled, Cache

on, while (1) code

131

—

All peripheral

disabled, Cache

off, while (1) code

executing from

MRAM

135

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 82 of 295

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