PRSP0016JC-B datasheet(39/85 Pages) RENESAS

39 / 85 page

RL78/G16

2. ELECTRICAL SPECIFICATIONS (TA

= −40 to +85°C)

R01DS0431EJ0130

Rev.1.30

Page 39 of 85

May 19, 2025

(2)

Simplified SPI (CSI) mode (master mode, SCKp... internal clock output)

[TA =

−40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V]

Item

Symbol

Condition

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

≥ 4/f

CLK

2.4 V

≤ V

≤ 5.5 V

250

SCKp high-/low-level width

tKH1, tKL1

2.7 V

≤ V

≤ 5.5 V

tKCY1/2

− 18

2.4 V

≤ V

≤ 5.5 V

tKCY1/2

− 38

SIp setup time

(to SCKp

↑)Note 1

tSIK1

2.7 V

≤ V

≤ 5.5 V

2.4 V

≤ V

≤ 5.5 V

SIp hold time

(from SCKp

↑)Note 1

tKSI1

Delay time from SCKp

↓ to SOp

outputNote 2

tKSO1

C = 30 pFNote 3, Note 4

Note 1.

When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp

↓”

and the SIp hold time becomes “from SCKp

↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n =

Note 2.

When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes

“from SCKp

↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.

Note 3.

C is the load capacitance of the SCKp and SOp output lines.

Note 4.

External loads on P60

and P61 in the case of the SOp output line: R = 1 kΩ, C = 30 pF

(3)

Simplified SPI (CSI) mode (slave mode, SCKp... external clock input)

[TA =

−40 to +85°C, 2.4 V ≤ VDD ≤ 5.5V, VSS = 0V]

Item

Symbol

Condition

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY2

2.7 V

≤ V

≤ 5.5 V

6/fMCK

2.4 V

≤ V

≤ 5.5 V

6/fMCK and

also 500

SCKp high-/low-level width

tKH2,tKL2

2.4 V

≤ V

≤ 5.5 V

tKCY2/2

− 18

SIp setup time

(to SCKp

↑)Note 1

tSIK2

2.7 V

≤ V

≤ 5.5 V

1/fMCK + 20

2.4 V

≤ V

≤ 5.5 V

1/fMCK + 30

SIp hold time

(from SCKp

↑)Note 1

tKSI2

2.4 V

≤ V

≤ 5.5 V

1/fMCK + 31

Delay time from SCKp

↓ to SOp

outputNote 2

tKSO2

C = 30 pF

Note 3, Note 4

2.7 V

≤ V

≤ 5.5 V

2/fMCK + 50

2.4 V

≤ V

≤ 5.5 V

2/fMCK + 75

Note 1.

When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp

↓”

and the SIp hold time becomes “from SCKp

↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n =

Note 2.

When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes

“from SCKp

↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.

Note 3.

C is the load capacitance of the SOp output lines.

PRSP0016JC-B Datasheet(PDF) 39 Page - Renesas Technology Corp

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