SERCON410B datasheet(25/34 Pages) STMICROELECTRONICS

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CONTROL REGISTER ADDRESSES (Continued)

A6-1

Bit

Name

R/W

Value

Function

OCH

POLCYCCLK

R/W

Timing control triggered by rising edge of

CYC_CLK

Timing control triggered by falling edge of

CYC_CLK

CYCSTART

No function

Trigger timing control after TCYCSTART

(master)

RDTCNT

Do not read TCNT

Load TCNT to TCNTRD

12-15

NCYC

R/W

Number of communcation cycles triggered by

CYC_CLK or CYCSTART

0DH

0-7

HS_TIMEOUT

R/W

Handshake timeout for service channel

8-15

BUSY_TIMEOUT

R/W

BUSY timeout for service channel

0EH

0-4

MCLKDIV

R/W

Predivider value: fMCLK/1 MHz - 1

(reset value = 19)

5-7

(Not used)

8-12

MCLKST

R/W

Initial value for predivider

13-15

(Not used)

0FH

0-15

TSCYC0

R/W

SERCOS interface cycle time in

•s for

transmission block 0

10H

0-15

TSCYC1

R/W

SERCOS interface cycle time in

•s für

transmission block 1

11H

0-15

TCYCDEL

Time at which MST is received, ring delay

(master)

12H

0-15

TCNTLT

Stored value of TCNT time counter

13H

0-15

TCNTST

R/W

Initial value for TCNT time counter

14H

0-15

TCYCSTART

R/W

Delay in triggering timing control

15H

0-15

JTSCYC1

R/W

Receive time window for MST 1

16H

0-15

JTSCYC2

R/W

Receive time window for MST 2

17H

0-15

PROGERR_FL

Error flags

CLR_PROGERR_FL

Clear error flags

18H

0-15

JTRDEL1

R/W

Receive time window for data telegram 1

19H

0-15

JTRDEL2

R/W

Receive time window for data telegram 2

1AH

0-15

TINT0

R/W

Time at which time interrupt 0 and first edge

of CON_CLK occur

1BH

0-15

TINT1

R/W

Time at which time interrupt 1 and second

edge of CON_CLK occur

SERCON410B

21/30

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