ADATE320KCPZ datasheet(21/78 Pages) AD

No. de pieza	ADATE320KCPZ

Descripción Electrónicos	1.25 GHz Dual Integrated DCL with PPMU, Level Setting DACs, and On-Chip Calibration Registers

PDF	78 Pages

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Fabricante Electrónico	AD [Analog Devices]

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21 / 78 page

Data Sheet

ADATE320

SPECIFICATIONS

analog.com

Rev. C | 21 of 78

Table 14.

Parameter

Symbol

Min

Typ

Max

Unit

Test Level

Description

BUSY Release from SCLK

tBUSR

Propagation delay from qualifying SCLK edge to BUSY

release.

Width of Assert

tRMIN

Minimum width of asynchronous RST assert, 5 pF

external loading.

RST to SCLK Setup at Assert

tRS

1.5

Minimum setup time of RST release to next rising edge

of SCLK.

SCLK Cycles per SPI Word

tSPI

Cycles

Minimum number of SCLK rising edge cycles required

per valid SPI operation, including the minimum tCSAM

requirement between consecutive CS assertions.

Internal DAC Settling to Within ±2 mV from

BUSY Release

tDAC

µs

Settling time of internal analog DAC levels to within ±2

mV. Settling time is relative to the release of BUSY.1

1 The overall settling time may be dominated by the characteristics of an analog block (such as the PPMU or driver) and its respective mode setting (such as Range A or

Range B).

SPI TIMING DIAGRAMS

Figure 2. SPI Detailed Read/Write Timing Diagram

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