NRF52810-QFAA-R datasheet(66/483 Pages) NORDIC

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Power and clock management

5.3.7 Retained registers

A retained register is a register that will retain its value in System OFF mode and through a reset,

depending on reset source. See individual peripheral chapters for information of which registers are

retained for the various peripherals.

5.3.8 Reset behavior

Reset target

Reset source

CPU

Peripherals GPIO

Debuga

SWJ-DP

RAM

WDT

Retained

registers

RESETREAS

CPU lockup 5

Soft reset

Wakeup from System OFF

mode reset

x 6

x 7

Watchdog reset 8

Pin reset

Brownout reset

Power on reset

Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.

5.3.9 Registers

Base address

Peripheral

Instance

Description

Configuration

0x40000000

POWER

Power control

For 24 kB RAM variant, only RAM[0].x to

RAM[2].x registers are in use.

Table 14: Instances

Offset

Description

TASKS_CONSTLAT

0x078

Enable constant latency mode

TASKS_LOWPWR

0x07C

Enable low power mode (variable latency)

EVENTS_POFWARN

0x108

Power failure warning

EVENTS_SLEEPENTER 0x114

CPU entered WFI/WFE sleep

EVENTS_SLEEPEXIT

0x118

CPU exited WFI/WFE sleep

INTENSET

0x304

Enable interrupt

INTENCLR

0x308

Disable interrupt

RESETREAS

0x400

Reset reason

SYSTEMOFF

0x500

System OFF register

POFCON

0x510

Power failure comparator configuration

GPREGRET

0x51C

General purpose retention register

a All debug components excluding SWJ-DP. See Debug on page 50 chapter for more information about

the different debug components in the system.

5 Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible

in System OFF.

6 The Debug components will not be reset if the device is in debug interface mode.

7 RAM is not reset on wakeup from OFF mode, but depending on settings in the RAM register parts, or

the whole RAM, may not be retained after the device has entered System OFF mode.

8 Watchdog reset is not available in System OFF.

4430_161 v1.0

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