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NRF52811-QCAA-R Datasheet(PDF) 37 Page - Nordic Semiconductor

No. de pieza NRF52811-QCAA-R
Descripción Electrónicos  nRF52811
PDF  444 Pages
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Fabricante Electrónico  NORDIC [Nordic Semiconductor]
Página de inicio  https://www.nordicsemi.com/
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NRF52811-QCAA-R Datasheet(HTML) 37 Page - Nordic Semiconductor

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Core components
If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might
occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall
and wait for access to be granted, or lose data.
4.6.2 EasyDMA array list
EasyDMA is able to operate in Array List mode.
The Array List mode is implemented in channels where the LIST register is available.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other
in RAM.
The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in
the code example below using a READER EasyDMA channel as an example:
#define BUFFER_SIZE 4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3] __at__ 0x20000000;
MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &ReaderList;
MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA
uses the READER.MAXCNT register to determine when the buffer is full.
buffer[0]
buffer[1]
0x20000000 : ReaderList[0]
0x20000004 : ReaderList[1]
0x20000008 : ReaderList[2]
buffer[2]
buffer[3]
READER.PTR = &ReaderList
buffer[0]
buffer[1]
buffer[2]
buffer[3]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 6: EasyDMA array list
4.7 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is
resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are
assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to
the same slave device. The following applies:
4454_140 v1.0
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