ST10 datasheet(13/58 Pages) STMICROELECTRONICS

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ST10F163

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V.1.1 - Return values

After a single or double word programming com-

mand, R0 contains error code, R1 remains

unchanged, R2 will contain the data in Flash for

location Segment+Segment Offset (R0.[3:0] with

R1), R3 will contain the data in Flash for location

Segment+Segment Offset +2 (R0[3:0] with R1+2),

R4 to R15 remain unchanged.

After a multi-word programming command, R0

contains error code, R1 will contains the last seg-

ment offset address of the last written word in

flash (failing flash address if R0 is not equal to

zero), R2 and R3 are undefined, R4 to R15

remain unchanged.

After erasing command, only R4 to R15 remain

unchanged, R0 will contain error code, R1 to R3

are undefined.

After status read command, R0 contains error

code, R1 contains flash embedded revision, R2

and R3 contains circuit identifiers (R2 = #0787h

and R3 = #0101h for this device), R4 to R15

remain unchanged.

V.1.2 - Programming examples

Programming a double word:

Note

For easier coding, the standard data paging addressing scheme is overrides for the two MOV instruction of the Flash Trigger

Sequence (EXTS instruction).This also locked both standard and PEC interrupts and class A hardware traps. Must be replace by

ATOMIC instruction if standard DPP addressing scheme must be preserved.

Programming a block of data:

Address 01’9000h to 01’9FFEh (inclusive) is to be programmed. Source data (data to be copied into

flash) is located in external RAM from address 03’1000h (to 03’1FFEh, implicitly):

; code hereafter assumes that flash is mapped in segment 1

; i.e. bit ROMS1 = ‘1’ in SYSCON register

; Flash must also be enabled, i.e. bit ROMEN = ‘1’ in SYSCON.

MOV

R0, #PROGDW

; DD4xh: Double word programming command

R0, #01h

; Selects segment 1 in flash memory

MOV

R1, #00224h

; Address to be programmed is 01’0224h

MOV

R2, #03456h

; Data to be programmed at 01’0224h

MOV

R3, #04567h

; Data to be programmed at 01’0226h

MOV

R4, #050d

; 50ns is 20 MHz CPU clock frequency

MOV

R7, #08000h

; R7 used for Flash trigger sequence

#define FCR 08000h

; Flash Unlock Sequence: consists in two consecutive writes, with the direct

addressing mode and then the indirect addressing mode. FCR must represent an

even address in the active address space of the Flash memory, and Rwn can be

any unused word GPR (R6 to R15)loaded with a value resulting in the same even

address than FCR

EXTS

#1, #2

; flash can be mapped in segment 0 or 1

MOV

FCR, R7

; first part

MOV

[R7], R7

; second part

NOP

; WARNING: place 2 NOP operations after

NOP

; the Unlock sequence to avoid all possible

; pipeline conflict in STEAK programs

; code hereafter assumes that flash is mapped in segment 1

; i.e. bit ROMS1 = ‘1’ in SYSCON register

; Flash must also be enabled, i.e. bit ROMEN = ‘1’ in SYSCON.

MOV

R0, #PROGMW

; AA5xh: Multi word programming command

R0, #01h

; Selects segment 1 in flash memory

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