ST20-GP1 datasheet(82/116 Pages) STMICROELECTRONICS

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ST20-GP1

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ASCIntEnable register

The ASCIntEnable register enables a source of interrupt.

Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding bit in

the ASCIntEnable register is 1.

ASCControl

ASC base address + #0C

Read/Write

Bit

Bit ﬁeld

Function

2:0

Mode

ASC mode control

Mode2:0

Mode

000

RESERVED

001

8-bit data

010

RESERVED

011

7-bit data + parity

100

9-bit data

101

8-bit data + wake up bit

110

RESERVED

111

8-bit data + parity

4:3

StopBits

Number of stop bits selection

StopBits1:0

Number of stop bits

0.5 stop bits

1 stop bit

1.5 stop bits

2 stop bits

ParityOdd

Parity selection

Even parity (parity bit set on odd number of ‘1’s in data)

Odd parity (parity bit set on even number of ‘1’s in data)

LoopBack

Loopback mode enable bit

Standard transmit/receive mode

Loopback mode enabled

Run

Baud rate generator run bit

Baud rate generator disabled (ASC inactive)

Baud rate generator enabled

RxEnable

Receiver enable bit

Receiver disabled

Receiver enabled

15:9

RESERVED. Write 0, will read back 0.

Table 13.5 ASCControl register format

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