ST62T10C datasheet(28/70 Pages) STMICROELECTRONICS

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ST62T08C/T09C ST62T10C/T20C/E20C

INTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register (IOR)

The Interrupt Option Register (IOR) is used to en-

able/disable the individual interrupt sources and to

select the operating mode of the external interrupt

inputs. This register is write-only and cannot be

accessed by single-bit operations.

Address: 0C8h

—

Write Only

Reset status: 00h

Bit 7, Bits 3-0 = Unused.

Bit 6 = LES: Level/Edge Selection bit.

When this bit is set to one, the interrupt source #1

is level sensitive. When cleared to zero the edge

sensitive mode for interrupt request is selected.

Bit 5 = ESB: Edge Selection bit.

The bit ESB selects the polarity of the interrupt

source #2.

Bit 4 = GEN: Global Enable Interrupt. When this bit

is set to one, all interrupts are enabled. When this

bit is cleared to zero all the interrupts (excluding

NMI) are disabled.

When the GEN bit is low, the NMI interrupt is ac-

tive but cannot cause a wake up from STOP/WAIT

modes.

This register is cleared on reset.

3.4.4 Interrupt Sources

Interrupt sources available on the ST62E20C/

T20C are summarized in the Table 9 with associ-

ated mask bit to enable/disable the interrupt re-

quest.

Table 9. Interrupt Requests and Mask Bits

*Except ST62T08C

LES

ESB

GEN

Peripheral

Address

Mask bit

Masked Interrupt Source

Interrupt

vector

GENERAL

IOR

C8h

GEN

All Interrupts, excluding

NMI

TIMER

TSCR

D4h

ETI

TMZ: TIMER Overflow

Vector 3

A/D CONVERTER(*)

ADCR

D1h

EAI

EOC: End of Conversion

Vector 4

Port PAn

ORPA-DRPA

C4h-CCh

ORPAn-DRPAn

PAn pin

Vector 1

Port PBn

ORPB-DRPB

C5h-CDh

ORPBn-DRPBn

PBn pin

Vector 2

116

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