ST723246 datasheet(85/161 Pages) STMICROELECTRONICS

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ST72324

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.6 Low Power Modes

10.4.6.1 Using the SPI to wakeup the MCU from

Halt mode

In slave configuration, the SPI is able to wakeup

the ST7 device from HALT mode through a SPIF

interrupt. The data received is subsequently read

from the SPIDR register when the software is run-

ning (interrupt vector fetch). If multiple data trans-

fers have been performed before software clears

the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake up the ST7 from Halt

mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low

when the ST7 enters Halt mode. So if Slave selec-

tion is configured as external (see Section

10.4.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

10.4.7 Interrupts

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

Mode

Description

WAIT

No effect on SPI.

SPI interrupt events cause the device to exit

from WAIT mode.

HALT

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the MCU is woken up by

an interrupt with “exit from HALT mode” ca-

pability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the device.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of Transfer

Event

SPIF

SPIE

Yes

Master Mode Fault

Event

MODF

Yes

Overrun Error

OVR

Yes

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