Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Mexican  ▼
ALLDATASHEET.COM.MX

X  

ST7263B Datasheet(PDF) 84 Page - STMicroelectronics

No. de pieza ST7263B
Descripción Electrónicos  LOW SPEED USB 8-BIT MCU FAMILY WITH FLASH/ROM, UP TO 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I²C
PDF  132 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7263B Datasheet(HTML) 84 Page - STMicroelectronics

Back Button ST7263B Datasheet HTML 80Page - STMicroelectronics ST7263B Datasheet HTML 81Page - STMicroelectronics ST7263B Datasheet HTML 82Page - STMicroelectronics ST7263B Datasheet HTML 83Page - STMicroelectronics ST7263B Datasheet HTML 84Page - STMicroelectronics ST7263B Datasheet HTML 85Page - STMicroelectronics ST7263B Datasheet HTML 86Page - STMicroelectronics ST7263B Datasheet HTML 87Page - STMicroelectronics ST7263B Datasheet HTML 88Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 84 / 132 page
background image
ST7263B
84/132
I²C BUS INTERFACE (Cont’d)
I²C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM
Fast/Standard I²C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I²C mode
1: Fast I²C mode
Bits 6:0 = CC6-CC0
7-bit clock divider.
These bits select the speed of the bus (FSCL) de-
pending on the I²C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): FSCL <= 100kHz
FSCL = fCPU/(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): FSCL > 100kHz
FSCL = fCPU/(3x([CC6..CC0]+2))
Note: The programmed FSCL assumes no load on
SCL and SDA lines.
I²C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = D7-D0
8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
I²C OWN ADDRESS REGISTER (OAR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:1 = ADD7-ADD1
Interface address.
These bits define the I²C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
Bit 0 = ADD0
Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
70
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
70
D7
D6
D5
D4
D3
D2
D1
D0
70
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com