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ST72E311J4D0 Datasheet(PDF) 89 Page - STMicroelectronics

No. de pieza ST72E311J4D0
Descripción Electrónicos  8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
PDF  100 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72E311J4D0 Datasheet(HTML) 89 Page - STMicroelectronics

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ST72E311 ST72T311
6.4 RESET CHARACTERISTICS
(TA=-40...+125
oC and V
DD=5V±10% unless otherwise specified.
Note:
1) These values given only as design guidelines and are not tested.
6.5 OSCILLATOR CHARACTERISTICS
(TA = -40°C to +125°C unless otherwise specified)
6.6 PERIPHERAL CHARACTERISTICS
Notes:
1. The safe reset cannot be guaranted by the LVD when fosc is greater than 8MHz.
2. Based on characterisation results, not tested.
Symbol
Parameter
Condition s
Min
Typ 1)
Max
Unit
RON
Reset Weak Pull-up R
ON
VIN >VIH
VIN <VIL
20
60
40
120
80
240
k
Ω
tRESET
Pulse duration generated by watch-
dog and POR reset
1
µs
tPULSE
Minimum pulse duration to be ap-
plied on external RESET pin
10 1)
ns
Symbol
Parameter
Test Conditions
Value
Unit
Min.
Typ.
Max.
gm
Oscillator transconductance
2
9
mA/V
fOSC
Crystal frequency
1
16
MHz
tstart
Osc. start up time
VDD =5V±10%
50
ms
Low Voltage Detection Reset Electrical Specifications (Optio n)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VLVDUP
LVD Reset Trigger, VDD rising edge
fOSC = 8 MHz max
1).
3.6 2)
3.85
4.1
V
VLVDDOWN
LVD Reset Trigger, VDD falling edge
3.35
3.6
3.85
V
VLVDHYS
LVD Reset Trigger, hysteresis2)
250
mV
89



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