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ADN8102ACPZ-R7 Datasheet(PDF) 25 Page - Analog Devices

No. de pieza ADN8102ACPZ-R7
Descripción Electrónicos  3.75 Gbps Quad Bidirectional CX4 Equalizer
PDF  32 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADN8102ACPZ-R7 Datasheet(HTML) 25 Page - Analog Devices

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ADN8102
Rev. A | Page 25 of 32
Table 15. Symbol Definitions for Output Levels vs. Setting
Symbol
Formula
Definition
VOD
25 Ω × IDC
Peak differential output voltage
VOD p-p
25 Ω × IDC × 2 = 2 × VOD
Peak-to-peak differential output voltage
dVOCM_DC-COUPLED
25 Ω × ITOT/2 = VOD p-p/4 + (IPE/2 × 25)
Output common-mode shift
dVOCM_AC-COUPLED
50 Ω × ITOT/2 = VOD p-p/2 + (IPE/2 × 50)
Output common-mode shift
IDC
VOD/RTERM
Output current that sets output level
IPE
Output current used for PE
ITOT
IDC + IPE
Total transmitter output current
VH
VTTO − dVOCM + VOD/2
Maximum single-ended output voltage
VL
VTTO − dVOCM − VOD/2
Minimum single-ended output voltage
SELECTIVE SQUELCH AND DISABLE
Each transmitter is equipped with output disable and output
squelch controls. Disable is a full power-down state: the trans-
mitter current is reduced to zero and the output pins pull up
to VTTO, but there is a delay of approximately 1 μs associated
with re-enabling the transmitter. The output disable control is
accessed through the EN bit (Bit 5) of the OUT_A/OUT_B
configuration registers through the I2C control interface.
Squelch is not a full power-down state but a state in which only
the output current is reduced to zero and the output pins pull
up to VTTO, and there is a much smaller delay to bring back
the output current. The output squelch and the output disable
control can both be accessed through the OUT_A/OUT_B
squelch control registers, with the top nibble representing the
squelch control for one entire output port and the bottom
nibble representing the output disable for one entire output
port. The ports are disabled or squelched by writing 0s to the
corresponding nibbles. The ports are enabled by writing all 1s,
which is the default setting. For example, to squelch Port A,
Register 0xC3 must be set to 0x0F. The entire nibble must be
written to all 0s for this functionality.
Table 16. Squelch Programming
Name
Address
Data
Default
OUT_A/
OUT_B
Squelch
Control
0xC3,
0xE3
SQUELCH[3:0]
DISABLE[3:0]
0xFF



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