M41T93RMY6F datasheet(20/51 Pages) STMICROELECTRONICS

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Clock operation

M41T93

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3.4

Clock calibration

The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When

the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at

25°C.

The M41T93 design provides the following two methods for clock error correction.

3.4.1

Digital calibration (periodic counter correction)

This method employs the use of periodic counter correction by adjusting the ratio of the

100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100Hz divider

stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide

the input frequency to the fraction of seconds clock register. By adjusting the number of

512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed

down, as shown in Figure 12 on page 26.

When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the

digital calibration register (08h) and the sign bit is ‘1,’ (indicating positive calibration), the

100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512.

Since the 100 pulses are now being output in a shorter window, this has the effect of

speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when

the sign bit is ‘0,’ indicating negative calibration, the block outputs 100 pulses for every 513

input pulses. Since the 100 pulses are then being output in a longer window, this has the

effect of slowing down the clock by 1/512 seconds for each second the circuit is active.

The amount of calibration is controlled by using the value in the calibration register (N) to

generate the adjustment in one second increments. This is done for the first N seconds once

every eight minutes for positive calibration, and for N seconds once every sixteen minutes

for negative calibration (see Table 4 on page 21).

For example, if the calibration register is set to '100010,' then the adjustment will occur for

two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the

adjustment will occur for 3 seconds in every alternating minute.

The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital

calibration register (08h). These bits can be set to represent any value between 0 and 31 in

binary form. The sixth bit (DCS) is a sign bit; '1' indicates positive calibration, '0' indicates

negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)

cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034

ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments

in the calibration byte would represent +10.7 or –5.35 seconds per month, which

corresponds to a total range of +5.5 or –2.75 minutes per month.

Note:

The modified pulses are not observable on the frequency test (FT) output, nor will the effect

of the calibration be measurable real-time, due to the periodic nature of the error

compensation.

Positive digital calibration is performed on an eight minute cycle, therefore the value in the

calibration register should not be modified more frequently than once every eight minutes for

positive values of calibration. Negative digital calibration is performed on a sixteen minute

cycle, therefore negative values in the calibration register should not be modified more

frequently than once every sixteen minutes.

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