74ACT174

2/11

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

X : Don’t Care

LOGIC DIAGRAM

This logic diagram has not to be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

1

CLEAR

Asynchronous Master

Reset (Active LOW)

2, 5, 7, 10,

12, 15

Q0 to Q5

Flip-Flop Outputs

3, 4, 6, 11,

13, 14

D0 to D5

Data Inputs

9

CLOCK

Clock Input (LOW-to-HIGH,

Edge Trigger)

8

GND

Ground (0V)

16

Positive Supply Voltage

INPUTS

OUTPUT

FUNCTION

CLEAR

D

CLOCK

Q

L

X

X

L

CLEAR

HL

L

HH

H

HX

NO CHANGE