74VHCT138AMTR datasheet(1/12 Pages) STMICROELECTRONICS

No. de pieza	74VHCT138AMTR

Descripción Electrónicos	3 TO 8 LINE DECODER (INVERTING)

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

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December 2004

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HIGH SPEED: tPD = 7.6 ns (TYP.) at VCC = 5V

s

LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s

COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN.), VIL = 0.8V (MAX)

s

POWER DOWN PROTECTION ON INPUTS

& OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

s

IMPROVED LATCH-UP IMMUNITY

s

LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION

The 74VHCT138A is an advanced high-speed

CMOS 3 TO 8 LINE DECODER (INVERTING)

fabricated

with

sub-micron silicon gate and

double-layer metal wiring C2MOS technology.

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. When enable input G1 is held low or either

G2A or G2B is held high, the decoding function is

inhibited and all the 8 outputs go to high.

The three enable inputs are provided to ease

cascade connection and application of address

decoders for memory systems.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V since all

inputs are equipped with TTL threshold.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74VHCT138A

3 TO 8 LINE DECODER (INVERTING)

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHCT138AMTR

TSSOP

74VHCT138ATTR

TSSOP

SOP

Rev. 3

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74VHCT138AMTR Datasheet(PDF) 1 Page - STMicroelectronics

74VHCT138AMTR Datasheet(HTML) 1 Page - STMicroelectronics

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