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ST7LITE1XB Datasheet(PDF) 24 Page - STMicroelectronics |
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ST7LITE1XB Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 159 page  ST7LITE1xB 24/159 – The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range 1) Refer to Section 15.1 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. Figure 13. PLL Output Frequency Timing Diagram When the PLL is started, after reset or wake up from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 13 and 13.3.5 Internal RC Oscillator and PLL) Refer to section 7.6.4 on page 35 for a description of the LOCKED bit in the SICSR register. Note 1: It is possible to obtain fOSC = 4MHz in the 3.3V to 5.5V range with internal RC and PLL enabled by selecting 1MHz RC and x8 PLL and setting the PLLdiv2 bit in the PLLTST register (see section 7.6.4 on page 35). 4/8 x freq. LOCKED bit set tSTAB tLOCK input tSTARTUP t 1 |
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