ST72334J2TASLASHXXX datasheet(38/150 Pages) STMICROELECTRONICS

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POWER SAVING MODES (Cont’d)

10.4 ACTIVE HALT AND HALT MODES

Active Halt and Halt modes are the two lowest

power consumption modes of the MCU. They are

both entered by executing the HALT instruction.

The decision to enter either in Active Halt or Halt

mode is given by the MCC/RTC interrupt enable

flag (OIE bit in MCCSR register).

10.4.1 Active Halt Mode

Active Halt mode is the lowest power consumption

mode of the MCU with a real-time clock available.

It is entered by executing the HALT instruction

when the OIE bit of the Main Clock Controller Sta-

tus register (MCCSR) is set (see Section 13.2

"MAIN CLOCK CONTROLLER WITH REAL-TIME

CLOCK TIMER (MCC/RTC)" on page 53 for more

details on the MCCSR register).

The MCU can exit Active Halt mode on reception

of either an MCC/RTC interrupt, a specific inter-

rupt

(see

Table 6,

“Interrupt

Mapping,”

page 35) or a RESET. When exiting Active Halt

mode by means of a RESET or an interrupt, a

4096 CPU cycle delay occurs. After the start up

delay, the CPU resumes operation by servicing

the interrupt or by fetching the reset vector which

woke it up (see Figure 22).

When entering Active Halt mode, the I bit in the CC

if an interrupt is pending, the MCU wakes up im-

mediately.

In Active Halt mode, only the main oscillator and

its associated counter (MCC/RTC) are running to

keep a wake-up time base. All other peripherals

are not clocked except those which get their clock

supply from another clock generator (such as ex-

ternal or auxiliary oscillator).

The safeguard against staying locked in Active

Halt mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering Active Halt mode while the Watchdog is

active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

Figure 21. Active Halt Timing Overview

Figure 22. Active Halt Mode Flowchart

Notes:

1. Peripheral clocked with an external clock source

can still be active.

2. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from Active Halt mode

(such as external interrupt). Refer to Table 6, “In-

terrupt Mapping,” on page 35 for more details.

3. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

Halt mode

Active Halt mode

HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT 2)

CPU

OSCILLATOR

PERIPHERALS 1)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS 1)

IBIT

OFF

X 3)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 3)

4096 CPU CLOCK CYCLE

DELAY

(MCCSR.OIE=1)

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