STA680Q datasheet(21/43 Pages) STMICROELECTRONICS

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STA680

Operation and general remarks

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Operation and general remarks

4.1

Clock schemes

The STA680 needs an external clock source to feed the internal Phase Locked Loops

(PLLs) to generate all the frequency needed by its cores and peripherals. This reference

clock may be supplied in several ways thus offering flexibility in the development of the final

application:

●

The reference clock may be supplied through the use of an external crystal or as a

digital signal coming from an external IC.

●

The reference clock may have different frequencies and can be fed to the STA680

through different input pins.

The selection of the clock input mode is performed during the power-on phase of the device

by latching the value of the pins ADAT3, BLEND and DAC256X on the rising edge of the

RESET_N signal (see Chapter 4.2); this value shall be selected according to Table 3.

Table 3.

Reference clock configuration

[ADAT3, BLEND,

DAC256X]

Clock type

Input pin

Clock frequency

(MHz)

[0,0,0] (1)

Default setting.

Crystal

OSC_IN

28.224

[0,0,1]

Digital

OSC_IN or CLK_IN (2)

When using OSC_IN pin to input the reference clock the CLK_IN pin must be connected to ground and vice

versa.

23.3472

[0,1,0]

Digital

OSC_IN or CLK_IN (2)

36.48

[0,1,1]

Digital

OSC_IN or CLK_IN (2)

2.9184

[1,0,0]

Digital

BB1_BCK

10.4

[1,0,1]

Digital

BB1_BCK

10.8

[1,1,0]

Digital

BB1_BCK

14.112

[1,1,1]

Digital

AUDIO_IN_ABCK

2.9184

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