Rev.2.00, Feb.18.2005, page 1 of 8

HD74LS164

8-Bit Parallel-Out Serial-in Shift Register

REJ03D0448–0200

Rev.2.00

Feb.18.2005

This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit

complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the

first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them

determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but

only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of

the clock input.

Features

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LS164P

DILP-14 pin

PRDP0014AB-B

(DP-14AV)

P

—

HD74LS164FPEL

SOP-14 pin (JEITA)

PRSP0014DF-B

(FP-14DAV)

FP

EL (2,000 pcs/reel)

HD74LS164RPEL

SOP-14 pin (JEDEC)

PRSP0014DE-A

(FP-14DNV)

RP

EL (2,500 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Pin Arrangement

(Top view)

GND

1

2

3

4

5

6

7

14

8

9

10

11

12

13

A

B

CK

A

Clear

B

Clock

CLR

Outputs

Outputs

Serial

Inputs