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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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M30624FGPFP Datasheet(PDF) 32 Page - Renesas Technology Corp |
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M30624FGPFP Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 101 page  M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Rev.2.41 Jan 10, 2006 Page 32 of 96 REJ03B0001-0241 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write “0”. When read, its content is indeterminate. |
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