Rev.2.00 Mar 30, 2006 page 1 of 11

HD74HC620, HD74HC623

Octal Bus Transceivers (with inverted 3-state outputs)

Octal Bus Transceivers (with 3-state outputs)

REJ03D0636-0200

(Previous ADE-205-516)

Rev.2.00

Mar 30, 2006

Description

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control

function implementation allows for maximum flexibility in timing.

This device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the

logic levels at the enable inputs (

GBA and GAB).

The enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of

GBA and

GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and

all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at

their last states. The 8-bit codes appearing on the two sets of buses will be identical for the HD74HC623 or

complementary for the HD74HC620.

Features

• High Speed Operation: t

• High Output Current: Fanout of 15 LSTTL Loads (Q

• Wide Operating Voltage: V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: I

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HC620P

DILP-20 pin

PRDP0020AC-B

(DP-20NEV)

P

—

HD74HC620FPEL

HD74HC623FPEL

SOP-20 pin (JEITA)

PRSP0020DD-B

(FP-20DAV)

FP

EL (2,000 pcs/reel)

HD74HC620RPEL

HD74HC623RPEL

SOP-20 pin (JEDEC)

PRSP0020DC-A

(FP-20DBV)

RP

EL (1,000 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Function Table

Enable Inputs

Operation

GBA

GAB

HD74HC620

HD74HC623

L

L

B data to A bus

B data to A bus

H

H

A data to B bus

A data to B bus

H

L

Isolation

Isolation

L

H

B data to A bus, A data to B bus

B data to A bus, A data to B bus