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STV9427 Datasheet(PDF) 8 Page - STMicroelectronics

No. de pieza STV9427
Descripción Electrónicos  HIGH SPEED MULTISYNCH ON-SCREEN DISPLAY FOR MONITOR
PDF  20 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STV9427 Datasheet(HTML) 8 Page - STMicroelectronics

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I.4.2 - Look-up Table Registers
Color look-up table [CLUT] is read/write RAM table.
Mapping address is described in Chapter I.3.2.
The CLUT is splitted in 2 blocks of 8 bytes. Each
byte contains foreground and background informa-
tions as described below :
SHA
BR
BG
BB
FL
FR
FG
FB
SHA
: Shadowing
FL
: Flashing foreground
BR, BG, BB : Background color
FR, FG, FB : Foreground color
If SHA = 1 and BR = BG = BB = 0, the background
of the character is transparent.
Each block may store a different set of colors. One
block of colors may be used for the normal items
of the menu while the second block, with brighter
colors, may be used for selected items of the menu.
The block selection is done by programming bit
CLU3 of CLU[3:0] of the character descriptor
(see Table 1). It remains selected all the row long.
Bit CLU2, CLU1 and CLU0 of CLU[3:0] of the
character descriptor select the active color at the
beginning of the row.
The active color can be changed along the row,
using 8 control codes COL0 to COL7.
Each control code (COL0 to COL7) active a dedicated
color byte in the CLUT as described in Table 2.
Table 1 : CLUT Block Selection
CLU3
CLU[2:0]
Code
Name
Ram
@(hex)
Reset Value
(hex)
0
0
Col 0
@3FE0
07
1
Col 1
@3FE1
16
2
Col 2
@3FE2
25
3
Col 3
@3FE3
34
4
Col 4
@3FE4
43
5
Col 5
@3FE5
52
6
Col 6
@3FE6
61
7
Col 7
@3FE7
70
1
0
Col 0
@3FE8
70
1
Col 1
@3FE9
61
2
Col 2
@3FEA
52
3
Col 3
@3FEB
43
4
Col 4
@3FEC
34
5
Col 5
@3FED
25
6
Col 6
@3FEE
16
7
Col 7
@3FEF
07
Table 2 : CLUT Color Selection
Code
Name
Code Nbr
(h)
Color Look-up Table in
RAM
COL1
10
@ 3FE0 : Color 0
COL2
11
@ 3FE1 : Color 1
COL6
16
@ 3FE6 : Color 6
COL7
17
@ 3FE7 : Color 7
COL0
10
@ 3FE8 : Color 8
COL1
11
@ 3FE9 : Color 9
COL6
16
@ 3FEE : Color 14
COL7
17
@ 3FEF : Color 15
I.4.3 - Control Registers
LINE DURATION (Reset Value : 20h)
3FF0 VSP HSP LD6
LD5
LD4
LD3
LD2
LD1
VSP
: V-SYNC active edge selection
= 0, falling egde,
= 1, rising edge.
HSP
: H-SYNC active edge selection
= 0, falling egde,
= 1, rising edge.
LD[6:1] : LINE DURATION
LD0 = 0
LD1 = 2 periods of character
One character period is 12 pixels long.
TOP MARGIN (Reset Value : 60h)
3FF1
M8
M7
M6
M5
M4
M3
M2
M1
M[8:1] : TOP MARGIN height from the VSYNC reference
edge.
M0 = 0
M1 = 2 scan lines
Note : The top margin is displayed before the first strip of descriptor
list. It can be black if FBK of DISPLAY CONTROL register is
set or transparent if FBK is clear.
HORIZONTAL DELAY (Reset Value : 20h)
3FF2 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
DD[7:0] : HORIZONTAL DISPLAY DELAY from the
HSYNC reference edge to the 1
st pixel position
of the character strips.
Unit = 6 pixel periods. Minimum value is 08h.
First pixel position = [DD[7:0] - 6] x 6 + 54.
with DD[7:0] = 1,3,5 then the delay is 60 pixel.
FUNCTIONAL DESCRIPTION (continued)
STV9427 - STV9428 - STV9429
8/20



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