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H8S2245 Datasheet(PDF) 16 Page - Renesas Technology Corp

No. de pieza H8S2245
Descripción Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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H8S2245 Datasheet(HTML) 16 Page - Renesas Technology Corp

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Rev.3.00 Mar. 26, 2007 Page xvi of xlii
REJ09B0355-0300
Item
Page Revision (See Manual for Details)
10.2.3 Time Constant
Registers B0 and B1
(TCORB0, TCORB1)
367
Description amended
... Note, however, that comparison is disabled during the T2 state
of a TCORB write cycle. ...
10.2.5 Timer
Control/Status Registers 0
and 1(TCSR0, TCSR1)
370
Bit 7
Compare Match Flag B (CMFB)
Description amended
[Clearing conditions]
• Cleared by reading CMFB when CMFB = 1, then writing 0 to
CMFB
• When DTC is activated by CMIB interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
371
Bit 6
Compare Match Flag A (CMFA)
Description amended
[Clearing conditions]
• Cleared by reading CMFA when CMFA = 1, then writing 0 to
CMFA
• When DTC is activated by CMIA interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
10.6.1 Setting Module
Stop Mode
381
Section 10.6.1 added
11.2.2 Timer
Control/Status Register
(TCSR)
391
Bit 7
Overflow Flag (OVF)
Note
* added
[Clearing condition] Cleared by reading TCSR when OVF = 1,
then writing 0 to OVF
*
Note:
* When OVF is polled and the interval timer interrupt is
disabled, OVF = 1 must be read at least twice.
11.2.3 Reset
Control/Status Register
(RSTCSR)
393
Bit 7
Watchdog Timer Overflow Flag (WOVF)
Description amended
[Clearing condition] Cleared by reading RSTCSR when WOVF =
1, then writing 0 to WOVF
11.4 Interrupts
400
Description added
... whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
11.5.6 OVF Flag
Clearing in Interval Timer
Mode
402
Section 11.5.6 added



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