H8SLASH3003 datasheet(324/715 Pages) RENESAS

324 / 715 page

TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and

an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM

mode and up-counters in other modes.

TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or

by input capture to GRA or GRB (counter clearing function) in the same channel.

When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in

the timer status register (TSR) of the corresponding channel.

When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in

TSR of the corresponding channel.

The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either

word access or byte access.

Each TCNT is initialized to H'0000 by a reset and in standby mode.

10.2.8 General Registers (GRA, GRB)

The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.

Channel

Abbreviation

Function

GRA0, GRB0

Output compare/input capture register

GRA1, GRB1

GRA2, GRB2

GRA3, GRB3

GRA4, GRB4

A general register is a 16-bit readable/writable register that can function as either an output

compare register or an input capture register. The function is selected by settings in the timer I/O

control register (TIOR).

When a general register is used as an output compare register, its value is constantly compared

with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set

to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.

Output compare/input capture register; can be buffered by buffer

registers BRA and BRB

Bit

Initial value

Read/Write

R/W

306

H8/3003 Datasheet(PDF) 324 Page - Renesas Technology Corp