H8SLASH3003 datasheet(327/715 Pages) RENESAS

No. de pieza	H8/3003

Descripción Electrónicos	microcontroller (MCU)

PDF	715 Pages

Scroll/Zoom	100%

Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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327 / 715 page

Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.

Bit 6

Bit 5

CCLR1

CCLR0

Description

TCNT is not cleared

(Initial value)

TCNT is cleared by GRA compare match or input capture*1

TCNT is cleared by GRB compare match or input capture*1

Synchronous clear: TCNT is cleared in synchronization with other

synchronized timers*2

Notes: 1. TCNT is cleared by compare match when the general register functions as a compare

match register, and by input capture when the general register functions as an input

capture register.

2. Selected in the timer synchro register (TSNC).

Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges

when an external clock source is used.

Bit 4

Bit 3

CKEG1

CKEG0

Description

Count rising edges

(Initial value)

Count falling edges

—

Count both edges

When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.

Phase counting takes precedence.

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H8/3003 Datasheet(PDF) 327 Page - Renesas Technology Corp