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32170 Datasheet(PDF) 49 Page - Renesas Technology Corp |
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32170 Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 881 page ![]() 2 2-2 32170/32174 Group User's Manual (Rev. 2.1) CPU 2.1 CPU Registers 2.1 CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses. Especially, R14 is used as a link register, and R15 is used as a stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the Processor Status Word register (PSW)'s stack mode (SM) bit. 31 31 00 R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note) Note: The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the PSW's SM bit. R0 R1 R2 R3 R4 R5 R6 R7 Figure 2.2.1 General-purpose Registers |
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