TDA9105A datasheet(16/31 Pages) STMICROELECTRONICS

16 / 31 page

OPERATING DESCRIPTION (continued)

The PLL1 ensures the coincidence between the

leading edge of the synchro signal and a phase

reference obtained by comparison between the

sawtooth of the VCO and an internal DC voltage

adjustable between 2.4V and 4V (by Pin 15). So a

±45° phase adjustment is possible (see Figure 11).

20k

Ω

220nF

From

Phase

Comparator

NOR1

6.5V

H-Lock CAP

HLOCKOUT

Figure 15 : LOCK/UNLOCK Block Diagram

H Osc

Sawtooth

Phase REF1

H Synchro

1.6V

6.4V

2.4V<Vb<4V

0.75T

0.25T

Phase REF1 is obtained by comparison between the sawtooth and

a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures

the exact

coincidence between the signals phase REF and

HSYNS. A

± T/8 phase adjustment is possible.

Figure 14 : PLL1 Timing Diagram

The two VCO threshold can be filtered by connect-

ing capacitor on Pins 8-9.

The TDA9103 also includes a LOCK/UNLOCK

identification block which senses in real-time

whether the PLL is locked on the incoming horizon-

tal sync signal or not. The resulting information is

available on HLOCKOUT output (Pin 2). The block

diagram of the LOCK/UNLOCK function is de-

scribed in Figure 12.

The NOR1 gate is receiving the phase comparator

output pulses (which also drive the charge pump).

When the PLL is locked, on point A there is a very

small negative pulse (100ns) at each horizontal

cycle, so after R-C filter, there is a high level on

Pin 13 which force HLOCKOUT to high level (pro-

vided that HLOCKOUT is pulled up to VCC).

When the PLL is unlocked, the 100ns negative

pulse on A becomesmuch larger and consequently

the average level on Pin 13 will decrease. When it

reaches 6.5V, point B goes to low level forcing

HLOCKOUT output to “0”.

The status of Pin 13 is approximately the following :

- Near 0V when there is no H-SYNC,

- Between 0 and 4V with H-SYNC frequency differ-

ent from VCO,

- Between 4 and 8V when H-SYNC frequency

= VCO frequency but not in phase,

- Near to 8V when PLL is locked.

It is important to notice that Pin 13 is not an output

pin and must only be used for filtering purpose (see

Figure 12).

TDA9105A

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