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PSD913F2 Datasheet(PDF) 29 Page - STMicroelectronics

No. de pieza PSD913F2
Descripción Electrónicos  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  91 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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PSD913F2 Datasheet(HTML) 29 Page - STMicroelectronics

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PSD9XX Family
PSD935G2
28
The
PSD935G2
Functional
Blocks
(cont.)
Level 1
SRAM, I /O
Level 2
Secondary Flash Memory
Highest Priority
Lowest Priority
Level 3
Main Flash Memory
Figure 6. Priority Level of Memory and I/O Components
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 80C51 and compatible family of microcontrollers, can be configured to have separate
address spaces for code memory (selected using PSEN) and data memory (selected using
RD). Any of the memories within the PSD935G2 can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the PSD’s CSIOP
space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and main Flash in Data Space at boot, and
secondary Flash memory in Program Space at boot, and later swap main and secondary
Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
boot up and having the microcontroller change it when desired.
Table 11 describes the VM Register.
Bit 7
Bit 6* Bit 5*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIO_EN
FL_Data Boot_Data
FL_Code
Boot_Code SRAM_Code
0 = disable
**
0 = RD
0 = RD
0 = PSEN
0 = PSEN
0 = PSEN
PIO mode
can’t
can’t
can’t
can’t
can’t
access
access
access
access
access
Flash
Boot Flash
Flash
Boot Flash
SRAM
1= enable
**
1 = RD
1 = RD
1 = PSEN
1 = PSEN
1 = PSEN
PIO mode
access
access
access
access
access
Flash
Boot Flash
Flash
Boot Flash
SRAM
Table 11. VM Register
NOTE: Bits 6-5 are not used.



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