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TSA1002IF Datasheet(PDF) 16 Page - STMicroelectronics |
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TSA1002IF Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 19 page ![]() TSA1002 16/19 capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). EVAL1002 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 10. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: SFSR=+0.2dB for static parameters.- SFSR=-0.5dB for dynamic parameters. Figure 10 : Analog to Digital Converter characterization bench Sine wave Generator Power Sine Wave Generator ADC evaluation board Logic Analyzer Pulse Generator dataready data ck Vin HP8644B HP8644B HP8133A TLA704 |
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