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CS5364 Datasheet(PDF) 18 Page - Cirrus Logic

No. de pieza CS5364
Descripción Electrónicos  114 dB, 192 kHz, 4-Channel A/D Converter
PDF  41 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5364 Datasheet(HTML) 18 Page - Cirrus Logic

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18
DS625F3
CS5364
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL =30pF
Notes:
1.
Data must be held for sufficient time to bridge the transition time of CCLK.
2.
For fsck <1 MHz
Figure 6. SPI Timing
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
06.0
MHz
RST Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
CS High Time Between Transmissions
tcsh
1.0
μs
CCLK Low Time
tscl
66
ns
CCLK High Time
tsch
66
CDIN to CCLK Rising Setup Time
tdsu
40
CCLK Rising to DATA Hold Time
(Note 1)
tdh
15
CCLK Falling to CDOUT Stable
tpd
-
50
Rise Time of CDOUT
tr1
25
Fall Time of CDOUT
tf1
Rise Time of CCLK and CDIN
(Note 2)
tr2
100
Fall Time of CCLK and CDIN
(Note 2)
tf2
CS
CCLK
CDIN
CDOUT
RST
t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
t
pd



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