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CS47048 Datasheet(PDF) 16 Page - Cirrus Logic |
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CS47048 Datasheet(HTML) 16 Page - Cirrus Logic |
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16 / 34 page ![]() CS47048 Data Sheet Audio SOC Processor Family 16 Copyright 2008 Cirrus Logic DS787A7 5.8 Digital Switching Characteristics — Internal Clock Parameter Symbol Min Max Unit Internal DSP_CLK frequency1 CS47048-CQZ CS47048-DQZ 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. Fdclk - Fxtal 2 Fxtal 2.See Section 5.7. 150 150 MHz Internal DSP_CLK period1 CS47048-CQZ CS47048-DQZ DCLKP - 6.7 6.7 1/Fxtal 1/Fxtal ns |
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