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HV430 Datasheet(PDF) 8 Page - Supertex, Inc

No. de pieza HV430
Descripción Electrónicos  High Voltage Ring Generator
PDF  8 Pages
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Fabricante Electrónico  SUTEX [Supertex, Inc]
Página de inicio  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV430 Datasheet(HTML) 8 Page - Supertex, Inc

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Pin Description
VPP1
Positive high voltage supply.
VPP2
Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be
connected between VPP2 and VPP1.
VNN1
Negative high voltage supply.
VNN2
Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be
connected between VNN2 and VNN1.
VDD
Logic supply voltage.
SGnd
Low voltage logic ground.
PGnd
High voltage power ground.
PIN
Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET.
Internally pulled low.
NIN
Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET.
Internally pulled low.
ENABLE
Logic enable input. Logic high enables IC. Internally pulled low.
MODE
Logic mode input. 0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control NOUT
and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner.
(See Truth Table)
FAULT
Logic output. Fault is at logic low when either current limit sense pin, VPsen or VNsen, is activated. Remains
active until overcurrent condition clears or ENABLE=0 or RESET=0.
RESET
Power-on reset. A capacitor connected between this pin and ground determines the delay time between application
of VDD and when the device outputs are enabled. Low leakage tantalum recommended.
DEADBAND
A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions. Applicable
only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input
mode, tie to Vdd.
VPgate
Gate drive for external P-channel MOSFET.
VNgate
Gate drive for external N-channel MOSFET.
VPsen
Pulse by pulse over current sensing for P-Channel MOSFET.
VNsen
Pulse by pulse over current sensing for N-Channel MOSFET.
Pin Configuration
1
10
2
3
4
5
6
7
8
9
20
11
19
18
17
16
15
14
13
12
top view
SOW 20
VDD
Fault
Mode
PIN
NIN
Enable
Reset
Deadband
SGND
PGND
VPP2
VPP1
VPSEN
VPGATE
N/C
N/C
VNGATE
VNSEN
VNN1
VNN2
HV430
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
12/13/010
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.



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