Data Sheet #: TM026

Page 2 of 8

Rev: P03

Date: 4/25/06

Application

The STS-100 module provides Synchronous

Equipment Timing Source (SETS) function in a SONET/

SDH network element. It generates SONET/SDH

equipment clocks (SEC) and frame synchronization

clocks. The module supports Free run, Locked and

Holdover modes of operations. The module supports 14

input clocks and generates 11 different outputs. The

module also supports master/slave configuration, which

provides protection against single STS-100 failure. This

module is incorporated with a microprocessor port,

which provides access to the internal registers.

The STS-100 module is a platform that is designed to

support easy installation and upgrade paths of the

ACS8530 SETS chip from Semtech. For timing

diagrams and additional details, please refer to the

ACS8530 data sheet. For register assignments, please

refer to the ACS8530 data sheet.

This product is ROHS-5 compliant. ROHS-5

indicates that this product is ROHS compliant except for

lead from those manufacturers wishing to take the lead

exemption.

Functional Block Diagram

3 Selectable TTL/CMOS Outputs

1@1.544 - 25.92 MHz

1@1.544 - 51.84 MHz

1@1.544 - 2.048 MHz

77.76 MHz CMOS Output

2kHz MFrSync w/ 50:50 MSR

AMI 64 kHz/8 kHz Output

19.44 MHz CMOS Output

38.88 MHz CMOS Output

RDY

Interrupt

8kHz FrSync w/ 50:50 MSR

2 Selectable LVDS/PECLOutputs

1@ 1.544 - 311.04 MHz

1@ 1.544 - 155.52 MHz

ACS8530

SETS chip

12.8 MHz

OCXO

8 Bit Data

10 TTL/CMOS Configurable References

up to 100 MHz

Control Inputs

6.48 MHz Input

AMI (64 kHz/8 kHz)

AMI (64 kHz/8kHz)

2 Configurable LVDS/PECL Inputs up

to 155.52 MHz

2kMFr Sync Input

7 Bit Address

Pin Outs

Figure 2

Two QTH-030-03-H-D-A-K-TR connectors from SAMTEC® are used on the STS-100 Module. The

mating Part# is QSH-030-01-H-D-A-K-TR.