Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Mexican  ▼
ALLDATASHEET.COM.MX

X  

AX2000-1CS896 Datasheet(PDF) 48 Page - Actel Corporation

No. de pieza AX2000-1CS896
Descripción Electrónicos  Axcelerator Family FPGAs
PDF  226 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  ACTEL [Actel Corporation]
Página de inicio  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 48 Page - Actel Corporation

Back Button AX2000-1CS896 Datasheet HTML 44Page - Actel Corporation AX2000-1CS896 Datasheet HTML 45Page - Actel Corporation AX2000-1CS896 Datasheet HTML 46Page - Actel Corporation AX2000-1CS896 Datasheet HTML 47Page - Actel Corporation AX2000-1CS896 Datasheet HTML 48Page - Actel Corporation AX2000-1CS896 Datasheet HTML 49Page - Actel Corporation AX2000-1CS896 Datasheet HTML 50Page - Actel Corporation AX2000-1CS896 Datasheet HTML 51Page - Actel Corporation AX2000-1CS896 Datasheet HTML 52Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 226 page
background image
Axcelerator Family FPGAs
2- 34
v2.7
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5V bus standard (EIA/JESD8-6). The Axcelerator devices
support Class I. This requires a differential amplifier input buffer and a push-pull output buffer.
AC Loadings
Timing Characteristics
Table 2-40 • DC Input and Output Levels
VIL
VIH
VOL
VOH
IOL
IOH
Min,V
Max,V
Min,V
Max,V
Max,V
Min,V
mA
mA
-0.3
VREF-0.1
VREF+0.1
3.6
0.4
VCC-0.4
8
-8
Figure 2-20 • AC Test Loads
Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ) (V)
Cload (pF)
VREF-0.5
VREF+0.5
VREF
0.75
20
* Measuring Point = Vtrip
Test Point
20 pF
50
VTT
Table 2-42 • 1.5V HSTL Class I I/O Module
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.425V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
1.5V HSTL Class I I/O Module Timing
tDP
Input Buffer
1.84
2.10
2.47
ns
tPY
Output Buffer
4.93
5.62
6.61
ns
tICLKQ
Clock-to-Q for the I/O input register
0.67
0.77
0.90
ns
tOCLKQ
Clock-to-Q for the IO output register and the I/O
enable register
0.67
0.77
0.90
ns
tSUD
Data Input Set-Up
0.23
0.27
0.31
ns
tSUE
Enable Input Set-Up
0.26
0.30
0.35
ns
tHD
Data Input Hold
0.00
0.00
0.00
ns
tHE
Enable Input Hold
0.00
0.00
0.00
ns
tCPWHL
Clock Pulse Width High to Low
0.43
0.48
0.57
ns
tCPWLH
Clock Pulse Width Low to High
0.45
0.51
0.60
ns
tWASYN
Asynchronous Pulse Width
0.43
0.48
0.57
ns
tREASYN
Asynchronous Recovery Time
0.10
0.10
0.10
ns
tHASYN
Asynchronous Removal Time
0.00
0.00
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.23
0.27
0.31
ns
tPRESET
Asynchronous Preset-to-Q
0.23
0.27
0.31
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com