LTC2751ACUHF-16-PBF datasheet(9/20 Pages) LINER

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LTC2751

2751f

PIN FUNCTIONS

RCOM (Pin 1): Center Tap Point of RIN and REF. Normally

tied to the negative input of the external reference invert-

ing ampliﬁer.

RIN (Pin 2): Input Resistor for External Reference Inverting

Ampliﬁer. Normally tied to the external reference voltage

VREF and to ROFS (Pin 37). Typically 5V; accepts up to

±15V.

S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to

program and to read back the output range of the DAC.

IOUT2 (Pin 4): DAC Current Output Complement. Tie IOUT2

to GND.

NC (Pin 5): No Connection. Must be tied to GND, provides

necessary shielding for IOUT2.

D3-D11 (Pins 6-14): LTC2751-12 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D11 is the MSB.

D5-D13 (Pins 6-14): LTC2751-14 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D13 is the MSB.

D7-D15 (Pins 6-14): LTC2751-16 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D15 is the MSB.

VDD (Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.

Requires a 0.1µF bypass capacitor to GND.

GND (Pin 16): Ground. Tie to ground.

⎯C⎯L⎯R (Pin 17): Asynchronous Clear. When ⎯C⎯L⎯R is taken

to a logic low, the data registers are reset to the zero-volt

code for the present output range (VOUT = 0V).

MSPAN (Pin 18): Manual Span Control Pin. MSPAN is used

to conﬁgure the LTC2751 for operation in a single, ﬁxed

output range. When conﬁgured for single-span operation,

the output range is set via hardware pin strapping. The

span input and DAC registers are transparent and do not

respond to write or update commands.

To conﬁgure the part for single-span use, tie MSPAN

directly to VDD. If MSPAN is instead connected to GND

(SoftSpan conﬁguration), the output ranges are set and

veriﬁed by using write, update and read operations. See

Manual Span Conﬁguration in the Operation section.

MSPAN must be connected either directly to GND (Soft-

Span conﬁguration) or VDD (single-span conﬁguration).

D0-D2 (Pins 19-21): LTC2751-12 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

D0-D4 (Pins 19-23): LTC2751-14 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

D0-D6 (Pins 19-25): LTC2751-16 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

NC (Pins 22-27): LTC2751-12 Only. No Connection.

NC (Pins 24-27): LTC2751-14 Only. No Connection.

NC (Pins 26, 27): LTC2751-16 Only. No Connection.

⎯D/S (Pin 28): Data/Span Select. This pin is used to select

activation of the data or span I/O pins (D0 to D15 or S0

to S2, respectively), along with their respective dedicated

registers, for write or read operations. Update operations

ignore ⎯D/S, since all updates affect both data and span

registers. For single-span operation, tie ⎯D/S to GND.

READ (Pin 29): Read Pin. When READ is asserted high,

the data I/O pins (D0-D15) or span I/O pins (S0-S2)

output the contents of the selected register (see Table 1).

For single-span operation, readback of the span I/O pins

is disabled.

UPD (Pin 30): Update and Buffer Select Pin. When READ

is held low and UPD is asserted high, the contents of the

input registers (both data and span) are copied into their

respective DAC registers. The output of the DAC is updated,

reﬂecting the new DAC register values.

When READ is held high, the update function is disabled

and the UPD pin functions as a buffer selector—logic low

to select the input register, high for the DAC register. See

Readback in the Operation section.

⎯W⎯R (Pin 31): Active Low Write Pin. A Write operation

copies the data present on the data or span I/O pins (D0-

D15 or S0-S2, respectively) into the input register. When

READ is high, the Write function is disabled.

S0 (Pin 32): Span I/O Bit 0. Pins S0, S1 and S2 are used to

program and to read back the output range of the DAC.

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