11

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

* High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.

➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.

Characteristics

Sym

Min

Typ ‡

Max

Units

Test Conditions

1

Chip Select Setup Time

20

0

ns

2

Read/Write Setup Time

25

5

ns

3

Address Setup Time

25

5

ns

4

Fast

40

100

ns

Delay

Slow

2.7

7.2

cycles

C4i cycles

➀

5

Fast Write Data Setup Time

20

ns

6

Slow Write Data Delay

2.0

1.7

cycles

C4i cycles

➀

7

Read Data Setup Time

0.5

cycles

C4i cycles

8

Data Hold Time Read

20

ns

Write

20

10

ns

9

50

90

ns

10

Chip Select Hold Time

0

ns

11

Read/Write Hold Time

0

ns

12

Address Hold Time

0

ns

13

Acknow. Hold Time

10

60

80

ns

AC Electrical Characteristics † - Processor Bus (Figures 11 and 17)

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

2.4V

0.4V

0.8V (Read) 0.8V (Write)

2.4V (Read) 2.0V (Write)

DS

CS

A5

to

A0

DTA

D7

to

D0

R/W

Figure 17 Processor Bus