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CLOCKING ADCS WITH THE CDCE62002

jitter

total

SNR

20log

jitter

(4)

(

)

(

)

total

ADC

CLK

jitter

(5)

A D C

S N R

6 .0 2 N

1 .7 6

(6)

DataConverterJitterRequirements

100

110

120

130

140

100

1000

10000

InputBandwidth(MHz)

1ps

350fs

100fs

50fs

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample

clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly

implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation

trend often causes engineers working in communications system design to encounter the term “clock limited

performance”. Therefore, it is important to understand the impact of clock jitter on ADC performance. The

following equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter:

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample

clock:

With respect to an ADC with N-bits of resolution, ignoring total jitter, ADC quantization error, and input noise, the

following equation shows the relationship between resolution and SNR:

Figure 35 plots Equation 4 and Equation 6 for constant values of total jitter. When used in conjunction with most

ADCs, the CDCE62002 supports a total jitter performance value of <1ps.

Figure 35. Data Converter Jitter Requirements

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