TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

For a Write Register Request the length of the LREQ data stream is 17 bits as shown in Table 10 (see Table 2

for the bit field format).

Table 10. Write Request Format

Bit(s)

Name

Description

0

Start bit

Indicates the beginning of the transfer (always 1).

1-3

Request type

Always a 101 indicating that this is a write register request.

4-7

Address

The address of the phy register to be written to.

8-15

Data

The data that is to be written to the specified register address.

16

Stop bit

Indicates the end of the transfer (always 0).

The 3-bit request field is defined in Table 11.

Table 11. Request Field

LREQ1

LREQ2

LREQ3

Name

Description

0

0

0

ImmReq

Immediate request. When an idle is detected, the phy takes control of the bus

immediately (no arbitration)

0

0

1

IsoReq

Isochronous request. When an acknowledge gap is detected, the phy arbitrates for the

bus.

0

1

0

PriReq

Priority request. The phy arbitrates after a subaction gap and ignore fair protocol. PriReq

is used for cycle master request.

0

1

1

Fair/Urgent Req

Fair or urgent request. The phy arbitrates after a subaction gap using fair protocol.

Fair/Urgent Req is used for fair transfers with the request priority field differentiating fair

and urgent transfers for the backplane environment.

1

0

0

RdReg

Read register. Returns the specified register contents through a status transfer

1

0

1

WrReg

Write register. Writes to the specified register

1

1

1

1

0

1

Reserved

Reserved

LREQ Timing (each cell represents one clock sample time) is shown in Figure 4.

LReq0

LReq1

LReq2

LReq3

LReqn

Figure 4. LREQ Timing