DS3100_09 datasheet(2/227 Pages) MAXIM

2 / 227 page

DS3100

19-4546; Rev 9; 5/09

2 of 227

TABLE OF CONTENTS

1. STANDARDS COMPLIANCE ................................................................................................7

2. BLOCK DIAGRAM.................................................................................................................8

3. APPLICATION EXAMPLE .....................................................................................................9

4. DETAILED DESCRIPTION ..................................................................................................10

5. DETAILED FEATURES .......................................................................................................12

5.1 T0 DPLL FEATURES ....................................................................................................................12

5.2 T4 DPLL FEATURES ....................................................................................................................12

5.3 INPUT CLOCK FEATURES..............................................................................................................12

5.4 OUTPUT CLOCK FEATURES ..........................................................................................................13

5.5 REDUNDANCY FEATURES.............................................................................................................13

5.6 BITS TRANSCEIVER FEATURES....................................................................................................13

5.6.1

General ......................................................................................................................................... 13

5.6.2

Receiver ....................................................................................................................................... 13

5.6.3

Transmitter ................................................................................................................................... 14

5.7 COMPOSITE CLOCK I/O FEATURES...............................................................................................14

5.8 GENERAL FEATURES ...................................................................................................................14

6. PIN DESCRIPTIONS............................................................................................................15

7. FUNCTIONAL DESCRIPTION .............................................................................................24

7.1 OVERVIEW...................................................................................................................................24

7.2 DEVICE IDENTIFICATION AND PROTECTION....................................................................................25

7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION...........................................................25

7.4 INPUT CLOCK CONFIGURATION.....................................................................................................26

7.4.1

Signal Format Configuration......................................................................................................... 26

7.4.2

Frequency Configuration .............................................................................................................. 28

7.5 INPUT CLOCK QUALITY MONITORING ............................................................................................29

7.5.1

Frequency Monitoring................................................................................................................... 29

7.5.2

Activity Monitoring ........................................................................................................................ 29

7.5.3

Selected Reference Activity Monitoring........................................................................................ 30

7.5.4

Composite Clock Inputs................................................................................................................ 30

7.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ..................................................................31

7.6.1

Priority Configuration .................................................................................................................... 31

7.6.2

Automatic Selection Algorithm ..................................................................................................... 31

7.6.3

Forced Selection........................................................................................................................... 32

7.6.4

Ultra-Fast Reference Switching.................................................................................................... 32

7.6.5

External Reference Switching Mode ............................................................................................ 32

7.6.6

Output Clock Phase Continuity During Reference Switching....................................................... 33

7.7 DPLL ARCHITECTURE AND CONFIGURATION.................................................................................33

7.7.1

T0 DPLL State Machine ............................................................................................................... 33

7.7.2

T4 DPLL State Machine ............................................................................................................... 36

7.7.3

Bandwidth..................................................................................................................................... 37

7.7.4

Damping Factor ............................................................................................................................ 38

7.7.5

Phase Detectors ........................................................................................................................... 38

7.7.6

Loss of Phase Lock Detection...................................................................................................... 39

7.7.7

Phase Monitor and Phase Build-Out ............................................................................................ 40

7.7.8

Input to Output Phase Adjustment ............................................................................................... 41

7.7.9

Phase Recalibration ..................................................................................................................... 41

7.7.10 Frequency and Phase Measurement ........................................................................................... 41

7.7.11 Input Wander and Jitter Tolerance ............................................................................................... 42

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