CS2100-CP

20

DS840F1

5.4

PLL Clock Output

The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.

The driver can be set to high-impedance with the ClkOutDis bit.

The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the

clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state

CLK_OUT may then be unreliable during an unlock condition.

Figure 18. PLL Clock Output Options

5.5

Auxiliary Output

The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 19, to one of four signals: refer-

ence clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator

(Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is

then used to control the output driver type and polarity of the LOCK signal (see section 8.6.2 on page 28).

If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the

CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit.

Figure 19. Auxiliary Output Selection

Referenced Control

Register Location

ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 29

ClkOutDis .............................. “PLL Clock Output Disable (ClkOutDis)” on page 26

Referenced Control

Register Location

AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 26

AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 25

AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 28

PLL Locked/Unlocked

PLL Output

2:1 Mux

ClkOutDis

2:1 Mux

ClkOutUnl

0

PLL Clock Output Pin

(CLK_OUT)

0

1

0

1

PLL Clock Output

PLLClkOut

Frequency Reference Clock

(CLK_IN)

PLL Lock/Unlock Indication

(Lock)

Timing Reference Clock

(RefClk)

PLL Clock Output

(PLLClkOut)

4:1 Mux

Auxiliary Output Pin

(AUX_OUT)

AuxOutDis

AuxOutSrc[1:0]

AuxLockCfg