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ADCLK954/PCBZ Datasheet(PDF) 11 Page - Analog Devices

No. de pieza ADCLK954/PCBZ
Descripción Electrónicos  Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer
PDF  12 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADCLK954/PCBZ Datasheet(HTML) 11 Page - Analog Devices

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ADCLK954
Rev. A | Page 11 of 12
INPUT TERMINATION OPTIONS
VREF
VCC
VT
CLK
CLK
CONNECT VT TO VCC.
50Ω
50Ω
Figure 19. Interfacing to CML Inputs
VREF
VT
CONNECT VT TO VCC − 2V.
VCC – 2V
50Ω
50Ω
CLK
CLK
Figure 20. Interfacing to PECL Inputs
VREF
VT
CONNECT VT TO VREF.
50Ω
50Ω
CLK
CLK
Figure 21. AC Coupling Differential Signals Inputs, Such As LVDS
VREF
VT
CONNECT VT, VREF, AND CLK. PLACE A BYPASS
CAPACITOR FROM VT TO GROUND.
ALTERNATIVELY, VT, VREF, AND CLK CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
50Ω
50Ω
CLK
CLK
Figure 22. Interfacing to AC-Coupled Single-Ended Inputs



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