MPC8379ECVRALGA datasheet(59/114 Pages) FREESCALE

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MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Serial ATA (SATA)

15.1

Requirements for SATA REF_CLK

The reference clock is a single ended input clock required for the SATA interface operation. The AC

requirements for the SATA reference clock are listed in the Table 50.

Figure 42 shows the SATA reference clock timing waveform.

Figure 42. SATA Reference Clock Timing Waveform

15.2

Transmitter (Tx) Output Characteristics

This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA

interface.

Table 50. SATA Reference Clock Input Requirements

Parameter

Condition

Symbol

Min

Typical

Max

Unit

Notes

SD_REF_CLK/ SD_REF_CLK

frequency range

—tCLK_REF

—

100/125/150

—

MHz

SD_REF_CLK/ SD_REF_CLK

clock frequency tolerance

—tCLK_TOL

–350

+350

ppm

—

SD_REF_CLK/ SD_REF_CLK

reference clock duty cycle

Measured at 1.6V

tCLK_DUTY

—

SD_REF_CLK/ SD_REF_CLK

cycle to cycle Clock jitter (period

jitter)

Cycle-to-cycle at

ref clock input

tCLK_CJ

—

100

—

SD_REF_CLK/ SD_REF_CLK total

reference clock jitter, phase jitter

(peak-peak)

Peak-to-peak jitter

at ref clock input

tCLK_PJ

–50

—

+50

2, 3

Note:

1 Only 100/125/150 MHz have been tested, othe in between values will not work correctly with the rest of the system.

2 In a frequency band from 150 kHz to 15 MHz at BER of 10-12.

3 Total peak to peak Deterministic Jitter "D

J" should be less than or equal to 50 ps.

Ref_CLK

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