AT90SCR100 datasheet(25/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

• Bits 5..4 – EEPM1..0 : EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action will be trig-

gered when writing EEPE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 6-1.

While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be

reset to 00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written or

not.

If EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the

selected address.

If EEMPE is clear, setting EEPE will have no effect. When EEMPE has been written to one by

software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE

bit for the EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEPE bit must be written to one to write the value into the

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

This is performed by step 2. Step 2 is only relevant if the software contains a Boot Loader allow-

Table 6-1.

EEPROM Mode Bits

EEPM1

EEPM0

Programming

Time

Operation

3.4 ms TBC

Erase and Write in one operation (Atomic Operation)

1.8 ms TBC

Erase Only

1.8 ms TBC

Write Only

–

Reserved for future use

AT90SCR100 Datasheet(PDF) 25 Page - ATMEL Corporation

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