AT89LP428 datasheet(31/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

9.1

Interrupt Response Time

The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls

the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the

preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to

the appropriate service routine as the next instruction, provided that the interrupt is not blocked

by any of the following conditions: an interrupt of equal or higher priority level is already in prog-

ress; the instruction in progress is RETI or any write to the IE, IP, IPH, IE2, IP2 or IP2H registers;

the CPU is currently forced into idle by an IAP or FDATA write. Each of these conditions will

block the generation of the LCALL to the interrupt service routine. The second condition ensures

that if the instruction in progress is RETI or any access to IE, IP, IPH, IE2, IP2 or IP2H, then at

least one more instruction will be executed before any interrupt is vectored to. The polling cycle

is repeated at the last cycle of each instruction, and the values polled are the values that were

present at the previous clock cycle. If an active interrupt flag is not being serviced because of

one of the above conditions and is no longer active when the blocking condition is removed, the

denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once

active but not serviced is not remembered. Every polling cycle is new.

If a request is active and conditions are met for it to be acknowledged, a hardware subroutine

call to the requested service routine will be the next instruction executed. The call itself takes

four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an

interrupt request and the beginning of execution of the first instruction of the service routine.

A longer response time results if the request is blocked by one of the previously listed condi-

tions. If an interrupt of equal or higher priority level is already in progress, the additional wait time

depends on the nature of the other interrupt's service routine. If the instruction in progress is not

in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest

are only 5 cycles long. If the instruction in progress is RETI or an access to IE or IP, the addi-

tional wait time cannot be more than 9 cycles (a maximum of four more cycles to complete the

instruction in progress, plus a maximum of 5 cycles to complete the next instruction). Thus, in a

single-interrupt system, the response time is always more than 5 clock cycles and less than

14 clock cycles. See Figure 9-1 and Figure 9-2.

Figure 9-1.

Minimum Interrupt Response Time

Figure 9-2.

Maximum Interrupt Response Time

Clock Cycles

INT0

IE0

Instruction

LCALL

1st ISR Instr.

Cur. Instr.

Ack.

Clock Cycles

INT0

IE0

114

Instruction

RETI

5 Cyc. Instr.

LCALL

1st ISR Instr.

Ack.

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