ATtiny167-ESSZ datasheet(183/282 Pages) ATMEL

183 / 282 page

183

7728D–AVR–07/09

ATtiny87/ATtiny167

• Bit 0 - LRXOK: Receive Performed Interrupt

This bit generates an interrupt if its respective enable bit - LENRXOK - is set in

LINENIR.

– 0 = No Rx

– 1 = Rx Response complete.

The user clears this bit by writing 1, in order to reset this interrupt.

In UART mode, this bit is also cleared by reading LINDAT.

15.6.3

LIN Enable Interrupt Register - LINENIR

• Bits 7:4 - Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be

written to zero when LINENIR is written.

• Bit 3 - LENERR: Enable Error Interrupt

– 0 = Error interrupt masked,

– 1 = Error interrupt enabled.

• Bit 2 - LENIDOK: Enable Identifier Interrupt

– 0 = Identifier interrupt masked,

– 1 = Identifier interrupt enabled.

• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt

– 0 = Transmit performed interrupt masked,

– 1 = Transmit performed interrupt enabled.

• Bit 0 - LENRXOK: Enable Receive Performed Interrupt

– 0 = Receive performed interrupt masked,

– 1 = Receive performed interrupt enabled.

15.6.4

LIN Error Register - LINERR

• Bit 7 - LABORT: Abort Flag

– 0 = No warning,

– 1 = LIN abort command occurred.

This bit is cleared when LERR bit in LINSIR is cleared.

Bit

654

LENERR

LENIDOK

LENTXOK

LENRXOK

LINENIR

Read/Write

R/W

Initial Value

Bit

76543210

LABORT

LTOERR

LOVERR

LFERR

LSERR

LPERR

LCERR

LBERR

LINERR

Read/Write

RRRRRRRR

Initial Value

00000000

ATtiny167-ESSZ Datasheet(PDF) 183 Page - ATMEL Corporation

ATtiny167-ESSZ Datasheet(HTML) 183 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL